cmos-ccd 1h delay line for ntsc with pll description the cxl5005m/p are general-purpose ccd delay line ics which provide 1h delay time of ntsc. features low power consumption 90mw (typ.) small size package (14-pin sop, dip) low differential gain dg = 3% (typ.) input signal ampiitude 180 ire (= 1.28vp-p, max.) low input clock amplitude operation 200mvp-p (min.) built-in triple pll circuit built-in peripheral circuits (clock driver, timing generator, auto-bias and output circuits) functions 680-bit ccd register clock drivers autobias circuit sync tip clamp circuit sample-and-hold circuit pll (triple) structure cmos-ccd absolute maximum ratings (ta = 25?) supply voltage v dd 11 v supply voltage v cl 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxl5005m 400 mw cxl5005p 800 mw recommended operating conditions supply voltage v dd 9 5% v v cl 5 5% v recommended clock conditions input clock amplitude v clk 200mvp-p to 1.0vp-p (300mvp-p typ.) clock frequency f clk 3.579545mhz ?1 e88z40a79-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxl5005m/p cxl5005m 14 pin sop (plastic) cxl5005p 14 pin dip (plastic)
? 2 cxl5005m/p blook diagram and pin configuration f 2 f 1 1 0 n c 1 1 o u t 1 3 a u t o 1 4 i n v c l 8 9 c l k n c 6 v c o o u t 7 v c o i n 3 4 v d d 2 v c l v s s 1 c l a m p c i r c u i t v c o a u t o - b i a s c i r c u i t 1 / 3 c o u n t e r 6 8 0 b i t s h i f t r e g i s t e r o u t p u t & s / h ( 1 b i t ) p h a s e c o m p a r a t o r 1 2 f e e d c l o c k d r i v e r 5 p c o u t pin description pin no. symbol description impedance [ ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ss v cl vco in v dd pc out nc vco out v cl clk nc out feed auto in gnd 5v power supply vco input 9v power supply phase comparator output vco output 5v power supply clock input signal output feedback dc output autobias dc output signal input > 100k 5k 5k 5k 600 to 1k > 100k 10k > 100k
? 3 cxl5005m/p electrical characteristics (ta = 25 c, v dd = 9.0v, v cl = 5.0v, f clk = 3.58mhz, v clk = 300mvp-p sine wave, see "electrical characteristics test circuit") item symbol test condition sw condition measuring point min. typ. max. unit 1 2 ma ma db db % deg vp-p db v v v v 5.0 12.0 3.0 5.0 5.0 1.28 6.5 6.5 3.3 3.7 4.0 9.0 0.0 ?.1 3.0 3.0 60 5.0 5.0 2.3 2.7 ?.0 ?.0 55 3.5 3.5 1.3 1.7 a1 a2 v1 v1 s v2 v3 v4 v5 v6 a a b a a a a a a a b, c e f d d a 250khz, 1.28vp-p, sine wave input 250khz, 1.28vp-p, sine wave input ig = 20 log (output voltage [vp-p] / 1.28 [vp-p]) dissipation at 3.58mhz in relation to 250khz fg = 20 log (v 3.58mhz / v 250khz ) (note 1) 5-staircase wave input y = 140 ire (= 1.0vp-p) measure with vector scope (note 2) s: input = 250khz, 1.0vp-p output (vp-p) n: input = dc gnd output (vrms) 250khz, 1.28vp-p, sine wave input i dd i cl ig fg dg dp v in-ac s/n v in-dc v auto-dc v feed-dc v out-dc supply current insertion gain frequency response differential gain differential phase allowable input amplitude noise dc output voltage
? 4 cxl5005m/p s w 2 a b v b i a s 9 v a 1 5 v a 2 0 . 1 f c l k f c l k = 3 . 5 8 m h z v c l k = 3 0 0 m v p - p s i n e w a v e 0 . 1 f v 4 0 . 1 f v 5 v 3 s w 1 0 . 1 f 1 m a . b . c . d . e . f . l p f n o t e 3 ) 9 v 5 6 0 0 v 6 b p f n o t e 4 ) v 1 v 2 v e c t o r s c o p e s v s s i n a u t o f e e d o u t c x l 5 0 0 5 m / p 1 1 1 2 1 3 1 4 v c l v c o i n v d d 4 2 3 1 1 0 0 k 5 p c o u t n c v c o o u t 7 6 n c c l k v c l 8 9 1 0 5 6 k 1 5 0 0 0 . 0 1 f 2 s a 1 1 7 5 2 5 0 k h z , 1 . 2 8 v p - p s i n e w a v e 2 5 0 k h z , 3 0 0 m v p - p s i n e w a v e 3 . 5 8 m h z , 3 0 0 m v p - p s i n e w a v e 5 - s t a i r c a s e w a v e g r o u n d 2 5 0 k h z , 1 . 0 v p - p s i n e w a v e electrical characteristics test circuit
? 5 cxl5005m/p note 1) frequency response test condition v 3.58mhz (output signal voltage [vp-p] at 3.58mhz input) v 250khz (output signal voltage [vp-p] at 250khz input) set pin 14 (in) voltage [v] = v in-dc + 640mv. 3 . 5 8 m h z , 3 0 0 m v p - p s i n e w a v e 2 5 0 k h z , 3 0 0 m v p - p s i n e w a v e 6 4 0 m v ( a d j u s t w i t h v b i a s ) v i n - d c [ v ] note 2) differential gain and differential phase test condition 1 h 6 3 . 5 s 4 0 i r e 1 4 0 i r e ( 1 . 0 v p - p ) c h r o m a 4 0 i r e 5 - s t a i r c a s e w a v e s i g n a l d g a n d d p a r e m e a s u r e d a t o u t p u t s p o i n t b y v e c t o r s c o p e . note 3) lpf frequency response 0 5 . 8 1 0 . 7 5 0 3 0 [ d b ] f r e q u e n c y [ m h z ] ( d e l a y t i m e 1 4 0 n s ) note 4) bpf frequency response 0 4 . 1 m 1 0 . 7 m 5 0 3 0 [ d b ] 2 0 0 5 0 f r e q u e n c y [ h z ]
? 6 cxl5005m/p application circuit c l k f c l k = 3 . 5 8 m h z v c l k = 3 0 0 m v p - p s i n e w a v e 5 6 0 0 0 . 0 1 f 9 v 5 v 0 . 1 f c x l 5 0 0 5 m / p 1 1 1 2 1 3 1 4 4 2 3 1 5 7 6 8 9 1 0 5 6 k 1 5 0 0 0 . 1 f 0 . 1 f c o m p o s i t e v i d e o s i g n a l i n p u t 0 . 1 f 1 m l . p . f 1 h d e l a y s i g n a l o u t p u t 2 s a 1 1 7 5 d e l a y t i m e 1 4 0 n s 9 v 5 v 7 5 . 6 k + 9 v 2 s c 4 0 3 3 f s c 5 . 6 k e x a m p l e o f p i n 7 ( v c o o u t p u t ) u s a g e application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . 0 1 2 3 2 0 0 2 0 4 0 6 0 4 i n p u t = 3 0 0 m v p - p 3 . 5 8 m h z , s i n e w a v e 0 1 2 3 4 . 7 5 . 0 5 . 3 4 i n p u t = 3 0 0 m v p - p 3 . 5 8 m h z , s i n e w a v e 0 1 2 3 8 . 5 9 . 0 9 . 5 4 i n p u t = 3 0 0 m v p - p 3 . 5 8 m h z , s i n e w a v e 1 0 1 2 0 6 0 3 2 0 2 0 4 0 i n p u t = 1 . 2 8 v p - p 2 5 0 k h z , s i n e w a v e f g f r e q u e n c y r e s p o n s e [ d b ] f r e q u e n c y r e s p o n s e v s . a m b i e n t t e m p e r a t u r e t a a m b i e n t t e m p e r a t u r e [ c ] v c l s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e v s . s u p p l y v o l t a g e f g f r e q u e n c y r e s p o n s e [ d b ] v d d s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e v s . s u p p l y v o l t a g e f g f r e q u e n c y r e s p o n s e [ d b ] t a a m b i e n t t e m p e r a t u r e [ c ] i g i n s e r t i o n g a i n [ d b ] i n s e r t i o n g a i n v s . a m b i e n t t e m p e r a t u r e example of representative characteristics
? 7 cxl5005m/p 1 0 1 2 4 . 7 5 . 0 5 . 3 3 4 3 2 1 2 0 2 0 6 0 0 0 4 0 0 2 3 4 1 0 k 1 0 0 k 1 m 1 4 . 7 5 . 3 5 . 0 4 3 2 1 0 8 . 5 9 . 5 9 . 0 4 3 2 1 0 0 1 2 3 8 . 5 9 . 0 9 . 5 1 i n p u t = 1 . 2 8 v p - p 2 5 0 k h z , s i n e w a v e g a i n [ d b ] i g i n s e r t i o n g a i n [ d b ] i n s e r t i o n g a i n v s . s u p p l y v o l t a g e v c l s u p p l y v o l t a g e [ v ] i g i n s e r t i o n g a i n [ d b ] i n s e r t i o n g a i n v s . s u p p l y v o l t a g e v d d s u p p l y v o l t a g e [ v ] d g d i f f e r e n t i a l g a i n [ % ] d g d i f f e r e n t i a l g a i n [ % ] d i f f e r e n t i a l g a i n v s . s u p p l y v o l t a g e v d d s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] d i f f e r e n t i a l g a i n v s . a m b i e n t t e m p e r a t u r e d i f f e r e n t i a l g a i n v s . s u p p l y v o l t a g e i n p u t = 1 . 2 8 v p - p 2 5 0 k h z , s i n e w a v e t a a m b i e n t t e m p e r a t u r e [ c ] d g d i f f e r e n t i a l g a i n [ % ] v c l s u p p l y v o l t a g e [ v ] t a = 2 5 c
? 8 cxl5005m/p package outline unit: mm 1 4 p i n d i p ( p l a s t i c ) 1 9 . 2 0 . 1 + 0 . 4 1 2 . 5 4 7 8 1 4 6 . 4 0 . 1 + 0 . 3 0 . 2 5 0 . 0 5 + 0 . 1 7 . 6 2 0 t o 1 5 3 . 7 0 . 1 + 0 . 4 0 . 5 m i n 0 . 5 0 . 1 3 . 0 m i n 1 . 2 0 . 1 5 s o n y c o d e e i a j c o d e j e d e c c o d e d i p - 1 4 p - 0 1 d i p 0 1 4 - p - 0 3 0 0 s i m i l a r t o m o - 0 0 1 - a h p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 0 . 9 g cxl5005m 1 4 p i n s o p ( p l a s t i c ) 9 . 9 0 . 1 + 0 . 4 0 . 4 5 0 . 1 1 . 2 7 7 . 9 0 . 4 5 . 3 0 . 1 + 0 . 3 6 . 9 0 . 5 0 . 2 0 . 2 0 . 0 5 + 0 . 1 0 . 1 0 . 0 5 + 0 . 2 1 . 8 5 0 . 1 5 + 0 . 4 m 0 . 2 4 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y s o p - 1 4 p - l 0 1 s o p 0 1 4 - p - 0 3 0 0 0 . 2 g 1 7 1 4 8 0 . 1 5 cxl5005p
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